The present invention relates to the field of data processing systems, specifically to the field of arithmetic apparatus and methods for performing arithmetic operations within data processing systems.
Decimal arithmetic operations have been implemented in prior art large scale digital processing systems. However, the apparatus used in large scale systems requires expensive hardware and requires extensive space. Decimal arithmetic operations have been performed within relatively small scale systems in microprocessors which generally may be two orders of magnitude smaller in scale then large scale systems. Because of the small size of microprocessors the hardware for implementing decimal arithmetic functions must be proportionately smaller and less elaborate than their counterparts in large systems. Prior art microprocessors utilize nine's or ten's complement addition and subtraction making addition and subtraction excessively complex to implement and understand, and difficult to use and manipulate. Although some microprocessors have performed BCD arithmetic methods in a sign magnitude representation, they have not utilized a binary adder to operate on multiple digits simultaneously. Thus there is a need for an apparatus and method for packed BCD sign magnitude arithmetic operations wherein the data remains in true digital decimal format and is implemented with a minimum of electronic circuitry.